The present invention relates to a new and improved pre-clean chamber for use in high vacuum sputtering systems for the deposition and/or etching of material on a wafer in the manufacture of integrated circuits.
High vacuum sputtering systems for the deposition and/or etching of material on a wafer in the manufacture of integrated circuits are well known. In particular, plasma vapor deposition (xe2x80x9cPVDxe2x80x9d) is used to deposit thin metal films for interconnect metalization on semiconductor wafers. PVD systems are typically automated systems that employ a plurality of processing chambers. Known PVD systems typically comprise a first air lock loading chamber in which cassettes containing a plurality of wafers to be processed are placed and from which the wafers are transported to a second vacuum chamber (or transportation chamber) by any suitable conveyor. Subsequently, the wafers are placed on a rotating table or stage in the plasma vapor deposition chamber. After the deposition process, the processed wafers are again transported back through the transportation chamber, to the loading chamber, and then back into the cassette for further handling/processing.
Prior to the PVD process, the wafers undergo a pre-clean process in a pre-clean chamber to remove any chemical residue or oxide which maybe formed when the wafer is exposed to atmosphere. Any chemical residue or oxide which remains on the wafer can act as a dielectric shield and impede the PVD film from uniformly adhering to the surface. The pre-clean chamber applies a light, non-selective, non-reactive plasma etch to the wafer to remove chemical residue remaining on the wafer surface. It also removes the thin layer (20-150 angstroms) of oxide which is formed when the wafer is exposed to atmosphere.
FIG. 1 illustrates a pre-clean chamber of the prior art. A chamber 100 comprises a base 102 and a chamber wall 104 that includes a wafer port (not shown) for receiving a wafer W in chamber 100. Once introduced into chamber 100 from the transport chamber (not shown) under vacuum, wafer W is transferred to a wafer lift 106, which is comprised of a wafer pedestal 108, an insulator 110, an insulator base 118, a shaft 120 and a bellows assembly 112. Wafer W is seated upon wafer pedestal 108 comprising an RF-biased, disk-shaped platform made from aluminum, titanium or other non-reactive metal. Wafer pedestal 108 is supported and insulated by insulator 110. Insulator 110 is generally a one-piece insulator, preferably comprising a non-reactive insulative material such as ceramic or quartz. Insulator 110 insulates the sides and bottom of wafer pedestal 108 and collimates the RF power to the top surface of wafer pedestal 108 and, hence, through wafer W. Insulator 110 is supported by insulator base 118. Shaft 120 supports wafer pedestal 108, insulator 110 and insulator base 118 and moves wafer W vertically between a release position, where wafer W is introduced from and is removed to the transport chamber, and a processing position, where wafer W is maintained during the etching process. Bellows assembly 112 surrounds shaft 120 and isolates shaft 120 when chamber 100 is under vacuum. Chamber cover 116 covers chamber 100 and seals chamber 100 during wafer processing.
During pre-clean processing, RF power is supplied to chamber 100. Gas inlet 114 introduces argon gas or other appropriate gases into the chamber for the pre-clean etching. RF power is then supplied to chamber 100, causing high voltage and high current to strike an argon plasma in the chamber. When the RF power is supplied to chamber 100, the bottom surface of chamber lid 116 acts as an anode and wafer pedestal 108 acts as a cathode. Positively charged argon ions are attracted to the negatively charged wafer pedestal 108. These ions bombard wafer W on wafer pedestal 108 and vertically etch the wafer surface.
FIGS. 2 and 3 illustrate a typical configuration for gas inlet 114. Gas inlet 114 comprises a gas trench 200 into which argon gas is introduced. Gas trench cover 202 is coupled to gas trench 200 and comprises a plurality of channels 204 that direct the gas introduced into gas trench 200 into focused streams that are introduced into chamber 100. Channels 204 are evenly spaced in gas trench cover 202 to provide even distribution of the gas in chamber 100. Because the channels 204 are vertical, the gas streams produced tend to bombard the chamber cover 116. If any oxide or other particulates have adhered to chamber cover 116 during a previous etch process, the gas streams may dislodge those particulates. The dislodged particulates may subsequently adhere to the surface of the wafer or settle back onto gas trench cover 202 only to be dislodged during a subsequent etch process, thereby compromising film properties of the PVD film to the surface of wafer W during subsequent PVD processing.
FIG. 4 illustrates a typical insulator 110 of the prior art. Insulator 110 is manufactured in one piece from quartz, ceramic or other appropriate insulating material. It is undesirable to have any significant portion of wafer pedestal 108 exposed to the chamber environment, as wafer pedestal 108 may be etched during the etch process, thereby releasing metal particles into the chamber. Consequently, insulator 110 preferably completely insulates the bottom and side surfaces of wafer pedestal 108. A one-piece insulator, however, poses several problems. First, the insulator surfaces are etched away during each etching process, thus exposing wafer pedestal 108 to the plasma. Insulator 110 can only be used for a certain number of etch cycles before its surface is so degraded that it must be replaced. Consequently, because insulator 110 is a relatively expensive component of the system, operational costs are high.
In addition, during the etch process, oxide and other particulates are released from the wafer and can be deposited on the insulator. This poses an additional problem as these particulates can be dislodged from the insulator during later processes and can adhere to the surface of other wafers, thus reducing device performance. Insulator 110 is typically manufactured with a roughened or course surface to absorb such particulates, although particulates can accumulate to such an extent that they can easily be dislodged from insulator 110 during etching. Consequently, it becomes necessary to clean and resurface insulator 110 between uses. However, subsequent cleaning and resurfacing of insulator 110 can create cracks in the insulator, resulting in degradation of the tolerances of the insulator and exposing wafer pedestal 108 and the bottom surface of wafer W to the etch process.
Referring again to FIG. 1, bellows assembly 112 of wafer lift 106 is generally designed in an accordion-like fashion, and is manufactured from a non-reactive metal such as stainless steel. During etching, oxide and other chemical residue particulates which are etched from the wafer tend to settle on chamber walls 104, chamber base 102 and bellows assembly 112. Because chamber walls 104 and base 102 remain stationary and are not subject to gas inlet streams, dislodgment of particulates from these structures during a subsequent etch procedure does not pose a significant problem. However, bellows assembly 112 expands and contracts as shaft 120 moves wafer lift 106 in a vertical direction; such movement may cause dislodgment of particulates deposited from a previous etch processes. Again, such particles can adhere to the surface of the wafer, adversely affecting the film properties of subsequent PVD processing.
Accordingly, there is a need for pre-clean chamber in a semiconductor processing system that minimizes the generation of particulates during processing, and which thereby increases the uniformity of subsequent PVD processes while decreasing operational costs.
The present invention concerns an improved pre-clean chamber of a semiconductor processing system that minimizes the generation of particulates during processing, thereby increasing the uniformity of a subsequent PVD process while decreasing operational costs. The improved pre-clean chamber comprises a base, a chamber wall, and a chamber cover. A gas suitable for etching a semiconductor wafer is introduced into the chamber via a gas inlet trench. A gas trench cover directs the gas from the gas inlet trench into streams that are focused up and towards the center of the chamber to reduce the extent to which the gas bombards the chamber cover dislodging particulates that may have adhered to the cover during a previous etch process.
In accordance with a preferred embodiment of the present invention, the improved pre-clean chamber also includes a wafer lift that supports the wafer in the pre-clean chamber and moves it vertically from a release position to a processing position. The wafer lift suitably comprises a wafer pedestal, an insulator, an insulator collar, an insulator base, a shaft, a bellows and a bellows cover. The wafer pedestal maybe manufactured from aluminum, titanium or other non-reactive metal and is RF-biased. The insulator, manufactured from ceramic or other non-reactive, insulating material, supports the wafer pedestal and insulates the bottom surface of the wafer pedestal.
In accordance with a further aspect of the present invention, the insulator collar may be manufactured from quartz, ceramic or other insulating material and may be a disposable item. The collar is supported by the insulator and, when coupled with the insulator, insulates the outside diameter surface of the wafer pedestal, thereby mitigating etching of the wafer pedestal during the etch process. Because the insulator collar can be discarded after an etch process, it does not have to be cleaned or resurfaced. Further, because it is not subjected to multiple etch processes, its surfaces are not degraded.
The shaft supports the wafer pedestal, insulator collar, insulator and insulator base. Annular bellows surround the shaft and isolate the shaft when the chamber is subjected to a vacuum. The bellows expand and contract as the shaft moves to raise and lower a wafer supported by the wafer pedestal. A bellows cover is fixedly attached to the insulator base to prevent particulates from adhering to the bellows during an etch process and dislodging from the bellows when the shaft raises and lowers the wafer.